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1 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz functional diagram features ? rf bandwidth: 25 - 3000 mhz ? 3.3 v supply ? maximum phase detector rate 100 mhz ? ultra low phase noise -110 dbc/hz in band typ. ? fractional figure of merit (fom) -226 dbc/hz ? 24-bit step size, resolution 3 hz typical ? exact frequency mode with 0 hz frequency error ? fast frequency hopping ? 40 lead 6x6 mm smt package: 36 mm 2 typical applications ? cellular infrastructure ? microwave radio ? wimax, wifi ? communications test equipment ? catv equipment ? dds replacement ? military ? tunable reference source for spurious-free performance www.datasheet.net/ datasheet pdf - http://www..co.kr/
2 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com general description the HMC832LP6GE is a 3.3 v, high performance, wide-band, fractional-n phase-locked-loop (pll) that features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 1500 mhz - 3000 mhz, and an integrated vco output divider (divide by 1/2/4/6.../60/62), that enables the HMC832LP6GE to generate continuous frequencies from 25 mhz to 3000 mhz. the integrated phase detector (pd) and delta-sigma modulator, capable of operating at up to 100 mhz, permit wider loop-bandwidths and faster frequency tuning, with excellent spectral performance. industry leading phase noise and spurious performance, across all frequencies, enable the HMC832LP6GE to minimize blocker effects, improve receiver sensitivity and transmitter spectral purity. low noise foor (-160 dbc/hz) eliminates any contribution to modulator/mixer noise foor in transmitter applications. the HMC832LP6GE is footprint compatible to the market leading hmc830lp6ge pll with integrated vco. it features all 3.3 v supply and an innovative programmable performance technology that enables the HMC832LP6GE to tailor current consumption and corresponding noise foor performance to individual applications by selecting either a low current consumption mode, or a high performance mode for an improved noise foor performance. additional features of the HMC832LP6GE include 12 db of rf output gain control in 1 db steps; output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; and a delta-sigma modulator exact frequency mode which enables users to generate output frequencies with 0 hz frequency error. parameter condition min. typ. max. units rf output characteristics output frequency 25 3000 mhz vco frequency at pll input 1500 3000 mhz rf output frequency at f vco 1500 3000 mhz output power rf output power at fundmental frequency = 2000 mhz across all frequencies see figure 22 max gain setting vco_reg 07h [3:0]=11d single-ended 7 dbm gain setting 6 vco_reg 07h [3:0]=6d differential 2 output power control range 1 db steps 12 db harmonics for fundamental mode fo mode at 2 ghz 2nd / 3rd / 4th -20/-29/-45 dbc fo/2 mode at 2ghz/2 = 1 ghz 2nd / 3rd / 4th -26/-10/-34 dbc fo/30 mode at 3 ghz/30 = 100 mhz 2nd / 3rd / 4th -33/-10/-40 dbc fo/62 mode at 1550 mhz/62 = 25 mhz 2nd / 3rd / 4th -40/-6/-43 dbc vco output divider vco rf divider range 1,2,4,6,8,...,62 1 62 electrical specifcations vppcp, vddls, vcc1, vcc2 = 3.3 v; rvdd, avdd, dvdd, vccpd, vcchf, vccps = 3.3 v min and max specifed across temp -40 c to 85 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
3 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz parameter condition min. typ. max. units pll rf divider characteristics 19-bit n-divider range (integer) max = 2 19 - 1 16 524,287 19-bit n-divider range (fractional) fractional nominal divide ratio varies (+/- 4) dynamically max 20 524,283 ref input characteristics max ref input frequency 350 mhz ref input level ac coupled [1] -6 12 dbm ref input capacitance 5 pf 14-bit r-divider range 1 16,383 phase detector (pd) [2] pd frequency fractional mode [3] dc 100 mhz pd frequency integer mode dc 100 mhz charge pump output current 0.02 2.54 ma charge pump gain step size 20 a pd/charge pump ssb phase noise 50 mhz ref, input referred 1 khz -143 dbc/hz 10 khz add 2 db for fractional -150 dbc/hz 100 khz add 3 db for fractional -152 dbc/hz logic inputs vsw 40 50 60 % dvdd logic outputs voh output high voltage dvdd v vol output low voltage 0 v output impedance 100 200 maximum load current 1.5 ma power supply voltages 3.3 v supplies avdd, vcchf, vccps, vccpd, rvdd,dvdd, vppcp, vddls, vcc1, vcc2 3.1 3.3 3.5 v electrical specifcations (continued) [1] measured with 100 external termination. see reference input stage section for more details. [2] slew rate of 0.5 ns/v is recommended, see reference input stage section for more details. frequency is guaranteed across process voltage and temperature from -40 c to +85 c. [3] this maximum pd frequency can only be achieved if the minimum n value is respected. eg. in the case of fractional mode, the maximum pd frequency = fvco/20 or 100 mhz, whichever is less. www.datasheet.net/ datasheet pdf - http://www..co.kr/
4 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com electrical specifcations (continued) parameter condition min. typ. max. units power supply currents high performance mode ( vco_reg 03h [1:0] =3d) [4] gain 11 ( vco_reg 07h [3:0] = 11d) single-ended output ( vco_reg 03h [3:2] = 2d) 2500 mhz 219 ma 800 mhz 230 gain 6 ( vco_reg 07h [3:0] = 6d) differential output ( vco_reg 03h [3:2] = 3d) 2500 mhz 226 800 mhz 237 gain 1 ( vco_reg 07h [3:0] = 1d) differential output vco_reg 03h [3:2] = 3d 2500 mhz 210 800 mhz 221 low current mode ( vco_reg 03h [1:0] =3d) [4] gain 6 ( vco_reg 07h [3:0] = 6d) differential output ( vco_reg 03h [3:2] = 3d) 2500 mhz 195 ma 800 mhz 205 gain 1 vco_reg 07h [3:0] = 1d differential output vco_reg 03h [3:2] = 3d 2500 mhz 180 800 mhz 192 power down - crystal off reg 01h =0, crystal not clocked 10 a power down - crystal on, 100 mhz reg 01h =0, crystal clocked 100 mhz 5 ma power on reset typical reset voltage on dvdd 700 mv min dvdd voltage for no reset 1.5 v power on reset delay 250 s vco open loop phase noise at fo @ 2 ghz [5] 10 khz offset -88 dbc/hz 100 khz offset -116 dbc/hz 1 mhz offset -139 dbc/hz 10 mhz offset -157 dbc/hz 100 mhz offset -162 dbc/hz [4] for detailed current consumption information please refer to figure 31 , and figure 32 . [5] gain setting = 6 ( vco_reg 07h [3:0] = 6d) in high performance mode ( vco_reg 03h [1:0] = 3d). www.datasheet.net/ datasheet pdf - http://www..co.kr/
5 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz parameter condition min. typ. max. units vco open loop phase noise at fo @ 2 ghz/2 = 1 ghz [5] 10 khz offset -93 dbc/hz 100 khz offset -122 dbc/hz 1 mhz offset -145 dbc/hz 10 mhz offset -159 dbc/hz 100 mhz offset -162 dbc/hz vco open loop phase noise at fo @3 ghz/30 = 100 mhz [5] 10 khz offset -110 dbc/hz 100 khz offset -139 dbc/hz 1 mhz offset -160 dbc/hz 10 mhz offset -163 dbc/hz 100 mhz offset -163 dbc/hz figure of merit (fom) floor integer mode ( figure 20 ) normalized to 1 hz -229 dbc/hz floor fractional mode ( figure 20 ) normalized to 1 hz -226 dbc/hz flicker (both modes) ( figure 20 ) normalized to 1 hz -268 dbc/hz vco characteristics vco tuning sensitivity at 2800 mhz measured with 1.5 v on vtune; see figure 29 24.6 mhz/v vco tuning sensitivity at 2400 mhz measured with 1.5 v on vtune; see figure 29 25.8 mhz/v vco tuning sensitivity at 2000 mhz measured with 1.5 v on vtune; see figure 29 25.2 mhz/v vco tuning sensitivity at 1600 mhz measured with 1.5 v on vtune; see figure 29 24.3 mhz/v vco supply pushing measured with 1.5 v on vtune 2.8 mhz/v electrical specifcations (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
6 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 1. typical closed loop integer phase noise [1] figure 2. typical closed loop fractional phase noise [1] figure 3. open loop vco phase noise at 1800 mhz figure 4. closed loop phase noise at 1800 mhz, divided by 1 to 62 [2] figure 5. free running vco phase noise at 3000 mhz figure 6. closed loop phase noise at 3000 mhz, divided by 1 to 62 [2] typical performance characteristics [1] measured with 50 mhz pd frequency, output gain of 6 ( vco_reg 07h [3:0] = 6d) and in high performance mode ( vco_reg 03h [1:0] = 3d). loop filter designs are provided in table 1 . phase noise integrated from 1 khz to 100 mhz. [2] pd frequency, loop flter bandwidth 75 khz (type 2 from table 1 ), only a subset of available output divide ratios is shown. full range of output divide values includes 1,2,4,6,8, ... 58, 60, 62 . high performance mode selected ( vco_reg 03h [1:0] = 3d). -170 -160 -150 -140 -130 -120 -110 -100 10 3 10 4 10 5 10 6 10 7 10 8 750 mhz, evm = -62.5db, or 0.075 % 1600 mhz, evm = -57db or 0.141% 2500 mhz, evm = -53.3db or 0.216% 875 mhz, evm = -64.8db or 0.058% 1600 mhz, evm = -59.8db or 0.102% 2500mhz, evm = -55.8db or 0.168% offset (hz) phase noise (dbc/hz) loop bw = 127 khz loop bw = 75 khz -170 -160 -150 -140 -130 -120 -110 -100 10 3 10 4 10 5 10 6 10 7 10 8 880 mhz, evm = -61.3 db or 0.086% 1605 mhz, evm = -57.5 db or 0.133% 2505 mhz, evm = -52 db or 0.251% 880 mhz, evm = -61.8 db or 0.081% 1605mhz, evm = -57.2 db or 0.138% 2505 mhz, evm = -53.9 db or 0.204% offset (hz) phase noise (dbc/hz) loop bw = 75 khz loop bw = 127 khz -170 -160 -150 -140 -130 -120 -110 -100 10 3 10 4 10 5 10 6 10 7 10 8 offset (hz) phase noise (dbc/hz) /1 /2 /4 /8 /16 /32 /62 -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 offset (hz) phase noise (dbc/hz) low current mode (vco_reg03h[10]=1d) high performance mode (vco_reg03h[10]=3d) -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 offset (hz) phase noise (dbc/hz) low current mode (vco_reg03h[10]=1d) high performance mode (vco_reg03h[10]=3d) -170 -160 -150 -140 -130 -120 -110 -100 10 3 10 4 10 5 10 6 10 7 10 8 offset (hz) phase noise (dbc/hz) /1 /2 /4 /8 /16 /32 /62 www.datasheet.net/ datasheet pdf - http://www..co.kr/
7 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz figure 7. fractional spurious performance at 904 mhz, exact frequency mode on [3] figure 8. fractional spurious performance at 1804 mhz, exact frequency mode on [4] figure 9. fractional spurious performance at 2118.24 mhz, exact frequency mode on [5] figure 10. fractional spurious performance at 2118.24 mhz, exact frequency mode off [6] figure 11. fractional spurious performance at 2646.96 mhz, exact frequency mode on [7] figure 12. fractional spurious performance at 2646.96 mhz, exact frequency mode off [8] -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -57 dbc integration bandwidth = 1 khz to 100 mhz snr = 54, evm = 0.199 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -57.45 dbc integration bandwidth = 1 khz to 100 mhz snr = 54.45 db, evm = 0.189 %,phase noise integration bandwidth 1 khz to 100 mhz -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -55.6 dbc integration bandwidth = 1 khz to 100 mhz snr = 52.6, evm = 0.234 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -56 dbc integration bandwidth = 1 khz to 100 mhz snr = 53 db, evm = 0.224 %, phase noise integration bandwidth 1 khz to 100 mhz -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -57 dbc integration bandwidth = 1 khz to 100 mhz snr = 54, evm = 0.199 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -57.45 dbc integration bandwidth = 1 khz to 100 mhz snr = 54.45 db, evm = 0.189 %,phase noise integration bandwidth 1 khz to 100 mhz -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -55.6 dbc integration bandwidth = 1 khz to 100 mhz snr = 52.6, evm = 0.234 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -56 dbc integration bandwidth = 1 khz to 100 mhz snr = 53 db, evm = 0.224 %, phase noise integration bandwidth 1 khz to 100 mhz -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -64.3 dbc integration bandwidth = 1 khz to 100 mhz snr = 61.3, evm = 0.086 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -65.5 dbc integration bandwidth = 1 khz to 100 mhz snr = 62.5 db, evm = 0.075 % phase noise integration bandwidth 1 khz to 100 mhz -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (khz) low current mode (vco_reg03h[10]=1d) ssb integrated phase noise = -58.7 dbc integration bandwidth = 1 khz to 100 mhz snr = 55.7, evm = 0.164 %, phase noise integration bandwidth 1 khz to 100 mhz high performance mode (vco_reg03h[10]=3d) ssb integrated phase noise = -59 dbc integration bandwidth = 1 khz to 100 mhz snr = 56 db, evm = 0.158 %, phase noise integration bandwidth 1 khz to 100 mhz [3] 122.88 mhz xtal, pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 from table 1 . [4] 122.88 mhz xtal, pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 from table 1 . [5] 122.88 mhz xtal, pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 from table 1 . [6] identical confguration to [5] with exact frequency mode turned off. [7] 122.88 mhz xtal, pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 from table 1 . [8] identical confguration to [7] with exact frequency mode turned off. www.datasheet.net/ datasheet pdf - http://www..co.kr/
8 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 13. low frequency performance [9] figure 14. typical spurious emissions at 2000.1 mhz, fixed reference [10] figure 15. typical spurious emissions at 2000.1 mhz, tunable reference [11] figure 16. typical spurious vs offset from 2 ghz, fixed vs. tunable reference [12] figure 17. open loop phase noise figure 18. open loop phase noise vs. temp. [9] 100 mhz xtal, pd frequency = 50 mhz, loop flter bandwidth 75 khz (type 2 from table 1 ), fractional mode. 50 mhz low pass filter used at the output of the HMC832LP6GE only for the 25 mhz curve. charge pump is set to maximum value. [10] 50 mhz fxed reference, 50 mhz pd frequency. the plot shows an integer boundary spur inside the loop flter bandwidth. all plls with integrated vcos exhibit integer boundary spurs at harmonics of the reference frequency. the plot shows the worst case spurious scenario where harmonic of the reference frequency (50 mhz) is within the loop flter bandwidth of the fundamental frequency of the HMC832LP6GE . [11] loop filter type 2 from table 1 . the tunable reference is used to change the reference frequency from 50 mhz in figure 14 to 47.5 mhz in fgure figure 15 in order to distance the harmonic of the reference frequency (spurious emissions) away from the fundamental output frequency of the HMC832LP6GE so that it is fltered by the loop flter. the internal HMC832LP6GE setup and divide ratios are changed in the opposite direction accordingly so that the HMC832LP6GE generates identical output frequency as in figure 14 without the spurious emissions inside the loop bandwidth. [12] the graph is generated by observing, and plotting, the magnitude of only the largest spur, at any offset, at each output frequency, while using a fxed 50 mhz reference and a tunable 47.5 mhz reference, and following procedure discussed in [11] . see HMC832LP6GE application information section for more details. contact hittite apps support to obtain the required confguration to achieve similar spurious performance throughout the operating range of the HMC832LP6GE . -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 2854 mhz 2453 mhz 2013 mhz 1587 mhz offset (hz) phase noise (dbc/hz) high performance mode on (vco_reg-3h[1:0] = 3d) -170 -160 -150 -140 -130 -120 -110 -100 100 1000 27c -40c 85c phase noise (dbc/hz) frequency (mhz) 300 30 100 mhz offset 1 mhz offset all modes low current mode high performance mode 100 khz offset all modes -170 -160 -150 -140 -130 -120 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) 55.55 mhz output 100 mhz output 25 mhz output -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -120 -110 -100 -90 -80 -70 -60 10 100 1000 phase noise (dbc/hz) output frequency (khz) 2000.010 2000.100 2001 typical spurious vs offset from 2 ghz, tunable reference ~47.5 mhz typical spurios vs offset from 2 ghz, fixed reference = 50 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
9 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz figure 19. single sideband integrated phase noise, high performance mode [13] figure 20. figure of merit figure 21. typical single-ended output power vs frequency (mid gain setting 6) figure 22. typical output power vs frequency and gain (single-ended) figure 23. typical rf output power at 2 ghz (single-ended) vs. temperature figure 24. rf output return loss -15 -10 -5 0 5 10 15 100 1000 return loss (vco_reg03h[5] = 0) return loss (vco_reg03h[5] = 1) frquency (mhz) output power (dbm) 3000 low current mode (vco_reg03h[1:0] = 1d) high performance mode (vco_reg03h[1:0] = 3d) -20 -15 -10 -5 0 5 10 15 20 100 1000 low current mode high performance mode frquency (mhz) output power (dbm) 3000 gain setting = 0 (vco_reg07h[3:0] = 0d) gain setting = 5 (vco_reg07h[3:0] = 5d) gain setting = 11 (vco_reg07h[3:0] = 11d) [13] loop filter type 2 from table 1 used. [14] using high performance mode ( vco_reg 03h [1:0] = 3d) [15] the HMC832LP6GE features programmable rf output return loss ( vco_reg 03h [5]) and 12 db of programmable gain ( vco_reg 07h [3:0]). maximum output power is achieved with high return loss setting ( vco_reg 03h [5] = 0) as shown in figure 21 . setting vco_reg 03h [5] = 1 improves return loss for applications that require it ( figure 21 ), at the cost of reduced rf output power ( figure 24 ). -240 -230 -220 -210 -200 10 2 10 3 10 4 10 5 10 6 normalized phase noise (dbc/hz) offset (hz) fom floor fom 1/f noise typ fom vs offset -90 -85 -80 -75 -70 -65 -60 -55 -50 100 1000 -40c 27c 85c ssb integrated phase noise (dbc) output frequency (mhz) 0.0141 0.0447 0.141 0.446 0.0045 evm (%) phase noise integrated from 10 khz to 20 mhz -6 -4 -2 0 2 4 6 8 10 024681 0 output power (dbm) 27c -40c 85c gain setting -30 -25 -20 -15 -10 -5 0 100 1000 output frequency (mhz) return loss (db) return loss 0 (vco_reg03h[5] = 0) return loss 1 (vco_reg03h[5] = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/
10 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 25. frequency settling after frequency change , autocal enabled [16] figure 26. phase settling after frequency change, autocal enabled [16] figure 27. frequency settling after frequency change , manual calibration [17] figure 28. phase settling after frequency change, manual calibration [17] -200 -150 -100 -50 0 50 100 150 200 0 20 40 60 80 100 120 140 160 time (us) phase error (degrees) settling time to < 10 degrees phase error -200 -150 -100 -50 0 50 100 150 200 0 20 40 60 80 100 120 140 160 time (us) phase error (degrees) settling time to < 10 degrees phase error note: loop filter bandwidth = 127 khz, loop filter phase margin = 61 degrees.this result is directly affected by loop filter design. faster settling time is possilbe with wider loop filter bandwidth and higher phase margin. 0 20 40 60 80 100 120 140 160 2.2 2.4 2.6 2.8 3 3.2 time (us) frequency error (ghz) settling time to < 10 degrees phase error 0 20 40 60 80 100 120 140 160 2.495 2.5 2.505 2.51 time (us) frequency error (ghz) settling time to < 10 degrees phase error note: loop filter bandwidth = 127 khz, loop filter phase margin = 61 degrees.this result is directly affected by loop filter design. faster settling time is possilbe with wider loop filter bandwidth and higher phase margin. [16] the HMC832LP6GE features an internal autocal process that seamlessly calibrates the HMC832LP6GE when a frequency change is executed. typical frequency settling time that can be expected after any frequency change ( reg 03h or reg 04h writes) is shown in figure 25 with autocal enabled ( reg 0ah [11] = 0). frequency hop of 5 mhz is shown in figure 25 , however the settling time is independent of the size of the frequency change. any size frequency size hop will have a similar settling time with autocal enabled. loop flter bw = 127 khz (type 1 in table 1 ). [17] for applications that require fast frequency changes, the HMC832LP6GE supports manual calibration that enables faster settling times. manual calibration needs to be executed only once for each individual HMC832LP6GE , at any temperature, and is valid across all temperature operating range of the HMC832LP6GE . more information about manual calibration is available in section 1.4.1.6 . frequency hop of 5 mhz is shown in figure 27 and figure 28 however the settling time is independent of the size of the frequency change. any size frequency size hop will have a similar settling time with autocal disabled ( reg 0ah [11] = 1). loop flter bw = 127 khz (type 1 in table 1 ). [18] the HMC832LP6GE features an internal autocal process that seamlessly calibrates the HMC832LP6GE when a frequency change is executed. once calibrated, at any temperature, the calibration setting holds across the entire operating range of the HMC832LP6GE (-40 c to +85 c ). figure 30 shows that the tuning voltage of the HMC832LP6GE is maintained within a narrow operating range for worst case scenarios where calibration was executed at one temperature extreme and the HMC832LP6GE is operating at the other extreme. 10 20 30 40 50 60 70 80 90 0 0.66 1.3 2 2.6 3.3 2854 mhz, tuning cap 15 2453 mhz, tuning cap 15 2013 mhz, tuning cap 15 1587 mhz, tuning cap 15 tuning voltage (v) kvco (mhz/v) 0 0.5 1 1.5 2 2.5 3 3.5 4 calibrated at 85c, measured at 85c calibrated at 85, measured at -40c calibrated at -40c,measured at -40c calibrated at -40c,measured at 85c calibrated at 27c, measured at 27c 1330 1520 1710 1900 2090 2280 2470 2660 2850 3040 tune voltage after calibration (v) vco frequency(mhz) fmin fmax figure 29. typical vco sensitivity figure 30. typical tuning voltage after calibration [15] www.datasheet.net/ datasheet pdf - http://www..co.kr/
11 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 220 222 224 226 228 230 232 234 -15 -12 -9 -6 -3 0 3 14 mhz square wave 25 mhz square wave 50 mhz square wave 100 mhz square wave fom (dbc/hz) reference power (dbm) 200 205 210 215 220 225 230 235 -20 -15 -10 -5 0 5 14 mhz sin 25 mhz sin 50 mhz sq 100 mhz sq reference power (dbm) fom (dbc/hz) figure 31. current consumption in single- ended output confguration [19] figure 32. current consumption in differential output confguration [19] figure 33. reference input sensitivity, square wave [20] figure 34. reference input sensitivity, sinusoidal wave [20] 160 170 180 190 200 210 220 230 240 500 1000 1500 2000 2500 3000 current consumption (ma) output frequency (mhz) low current consumption mode (vco_reg03h[1:0] = 1d) high performance mode (vco_reg03h[1:0] = 3d) fo fo/2 fo/4 fo/62 - - - - - output gain 0 db output gain 6 db -110 -90 -70 -50 -30 -10 100 1000 frquency (mhz) isolation (db) 3000 mute on (vco_reg03h[8:7] = 3d) signal on rf_n pin when rf_n pin off, rf_p pin on (vco_reg3h[3:2] = 1d), mute off (on only during vco calibration vco_reg03h[8:7] = 1d) both rf_n & rf_p pins off, (vco_reg3h[3:2] = 0d), mute off (on only during vco calibration vco_reg03h[8:7] = 1d) 180 200 220 240 260 500 1000 1500 2000 2500 3000 current consumption (ma) output frequency (mhz) low current consumption mode (vco_reg03h[1:0] = 1d) high performance mode (vco_reg03h[1:0] = 3d) fo fo/2 fo/4 fo/62 - - - - - output gain 0 db output gain 6 db figure 35. mute mode isolation [21] [19] output gain is confgured in vco_reg 07h [3:0]. differential or single-ended mode programmed in vco_reg 03h [3:2]. [20] measured from a 50 source with a 100 external resistor termination. [21] the HMC832LP6GE features a confgurable mute mode, along with the ability to independently turn off outputs on both rf_n and rf_p output pins. figure 35 shows isolation measured at the output when the mute mode is on ( vco_reg 03h [8:7] = 3d), and when the mute mode is off ( vco_ reg 03h [8:7] = 1d) with either both outputs disabled ( vco_reg 03h [3:2] = 0), or one output enabled and the other disabled ( vco_reg 03h [3:2] = 1d). www.datasheet.net/ datasheet pdf - http://www..co.kr/
12 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com table 1. loop filter designs used in typical performance characteristics graphs loop filter type loop filter bw (khz) loop filter phase margin c1 (pf) c2 (nf) c3 (pf) c4 (pf) r2 () r3 () r4 () loop filter design type 1 [22] 127 61 390 10 82 82 750 300 300 type 2 [23] 75 61 270 27 200 390 430 390 390 [22] loop filter type 1 is suggested to use for best integrated phase noise. it is designed for 50 mhz pd frequency, cp =2 ma in fractional mode. [23] loop filter type 2 is suggested to use for best far out phase noise. it is designed for 50 mhz pd frequency, cp =2 ma in fractional mode. pin descriptions pin number function description 1 avdd dc power supply for analog circuitry. 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 34, 37, 38 nc the pins are not connected internally; however. it is recommended to connect these pins to rf/dc ground externally. 3 vppcp power supply for charge pump analog section 4 cp charge pump output 7 vddls power supply for the charge pump digital section 10 rvdd reference supply 15 xrefp reference oscillator input 16 dvdd dc power supply for digital (cmos) circuitry 17 cen pll subsystem enable (no effect on the vco subsystem). connect to logic high for normal operation. 23 vtune vco varactor. tuning port input. 25 vcc2 vco analog supply 2 27 vcc1 vco analog supply 1 28 rf_n rf negative output 29 rf_p rf positive output 30 sen pll serial port enable (cmos) logic input 31 sdi pll serial port data (cmos) logic input 32 sck pll serial port clock (cmos) logic input 33 ld/sdo lock detect, or serial data, or general purpose (cmos) logic output (gpo) 35 vcchf dc power supply for analog circuitry 36 vccps dc power supply for analog prescaler 39 vccpd dc power supply for phase detector 40 bias external bypass decoupling for precision bias circuits. note: 1.920v 20mv reference voltage (bias) is generated internally and cannot drive an external load. must be measured with 10g meter such as agilent 34410a, normal 10m dvm will read erroneously. www.datasheet.net/ datasheet pdf - http://www..co.kr/
13 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz absolute maximum ratings avdd, rvdd, dvdd, vccpd, vcchf, vccps -0.3 v to +3.6 v vppcp, vddls, vcc1 -0.3 v to +3.6 v vcc2 -0.3 v to +3.6 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c maximum junction temperature 150 c thermal resistance (? jc ) (junction to case (ground paddle)) 9 c/w refow soldering peak temperature 260 c time at peak temperature 40 sec esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter condition min. typ. max. units temperature junction temperature [1] 125 c ambient temperature -40 85 c supply voltage avdd, rvdd, dvdd, vccpd, vcchf, vccps, vppcp, vddls, vcc1, vcc2 3.1 3.3 3.5 v [1] layout design guidlines set out in qualifcation test report are strongly recommended. www.datasheet.net/ datasheet pdf - http://www..co.kr/
14 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com outline drawing part number package body material lead finish msl rating package marking [1] HMC832LP6GE rohs-compliant low stress injection molded plastic 100% matte sn msl1 h832 xxxx [1] 4-digit lot number xxxx package information notes: 1. package body material: low stress injection molded plastic silica and silicon impregnated. 2. lead and ground paddle material: copper alloy. 3. lead and ground paddle plating: 100% matte tin. 4. dimensions are in inches [millimeters]. 5. lead spacing tolerance is non-cumulative. 6. pad burr length shall be 0.15mm max. pad burr height shall be 0.25mm max. 7. package warp shall not exceed 0.05mm. 8. all ground leads and ground paddle must be soldered to pcb rf ground. 9. refer to hittite application note for suggested pcb land pattern. www.datasheet.net/ datasheet pdf - http://www..co.kr/
15 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. evaluation pcb changing evaluation board reference frequency & cp current confguration the evaluation board is provided with a 50 mhz on-board reference oscillator, and type 1 loop flter confguration shown in table 1 (~127 khz bandwidth). the default register confguration fle included in the hittite pll evaluation software sets the comparison frequency to 50 mhz (r=1, ie. reg 02h = 1). as with all plls and pll with integrated vcos, modifying the comparison frequency or charge pump (cp) current will result in changes to the loop dynamics and ultimately, phase noise performance. when making these changes there are several items to keep in mind: ? cp offset current setting - refer to section 1.5.1 . ? ld confguration - refer to section 1.5.5 . to redesign the loop flter for a particular application, download hittites pll design software tool by clicking on the software download link on the HMC832LP6GE product page at www.hittite.com . hittite pll design enables users to accurately model and analyze performance of all hittite plls, plls with integrated vcos, and clock generators. it supports various loop flter topologies, and enables users to design custom loop flters and accurately simulate resulting performance. for evaluation purposes, the HMC832LP6GE evaluation board is shipped with an on-board, low cost, low noise (100 ppm), 50 mhz vcxo, enabling evaluation of most parameters including phase noise without any external references. exact phase or frequency measurements require the HMC832LP6GE to use the same reference as the measuring instrument. to accommodate this requirement, the HMC832LP6GE evaluation board includes the hmc1031ms8e ; a simple low current integer-n pll that can lock the on-board vcxo to an external 10 mhz reference input commonly provided by most test equipment. to lock the HMC832LP6GE to external 10 mhz reference simply connect the external reference output to j5 input of the HMC832LP6GE evaluation board and change the hmc1031ms8e integer divider value to 5 by changing the switch settings d1 = 1 (sw1-4 closed), and d0 = 0 (sw2-3 open), for more information please see the hmc1031ms8e data sheet. www.datasheet.net/ datasheet pdf - http://www..co.kr/
16 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com evaluation pcb schematic to view this evaluation pcb schematic please visit www.hittite.com and choose HMC832LP6GE from the search by part number pull down menu to view the product splash page. item contents part number evaluation kit HMC832LP6GE evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software, hittite pll design software) ekit01-hmc832lp6g evaluation order information HMC832LP6GE application information large bandwidth (25 mhz to 3000 mhz), industry leading phase noise and spurious performance, excellent noise foor (-160 dbc/hz), coupled with a high level of integration make the HMC832LP6GE ideal for a variety of applications; as an rf or if stage lo. figure 36. HMC832LP6GE in a typical transmit chain figure 37. HMC832LP6GE in a typical receive chain www.datasheet.net/ datasheet pdf - http://www..co.kr/
17 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz figure 38. HMC832LP6GE used as a tunable reference for HMC832LP6GE using the HMC832LP6GE with a tunable reference as shown in figure 38 , it is possible to drastically improve spurious emissions performance across all frequencies. example shown in figure 16 shows that it is possible to achieve spurious emissions as low as -108 dbc/hz at 2 ghz. please contact hittites application support to obtain detailed tunable reference confguration. power supply the HMC832LP6GE is a high performance low-noise device. in some cases phase noise and spurious performance may be degraded by noisy power supplies. to achieve maximum performance and ensure that power supply noise does not degrade the performance of the HMC832LP6GE it is highly recommended to use hittites low noise high psrr (power supply rejection ratio) regulator, the hmc1060lp3e . using the hmc1060lp3e lowers the design risk and cost, and ensures that the performance shown in typical performance characteristics can be achieved. power supply noise contribution to the pll output phase noise can easily be modelled in the hittite pll design tool. to download hittites pll design software tool, click on the software download link on the HMC832LP6GE product page at www.hittite.com programmable performance technology for low power applications that dont require maximum noise foor performance, the HMC832LP6GE features the ability to reduce current consumption by 50 ma (power consumption by 165 mw) at the cost of decreasing phase noise foor performance by ~5 db. high performance is enabled by writing vco_reg 03h [1:0] = 3d, and disabled (low current consumption mode enabled) by writing vco_reg 03h [1:0] = 1d. high performance mode improves noise foor performance at the cost of increased current consumption. resulting current consumption and phase noise foor performance are shown in figure 31 and figure 32 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
18 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 1.0 theory of operation the HMC832LP6GE pll with integrated vco is comprised of two sub-systems; pll subsystem and vco subsystem, as shown in figure 39 . figure 39. HMC832LP6GE pll and vco subsystems 1.1 pll subsystem overview the pll subsystem divides down the vco output to the desired comparison frequency via the n-divider (integer value set in reg 03h , fractional value set in reg 04h ), compares the divided vco signal to the divided reference signal (reference divider set in reg 02h ) in the phase detector (pd), and drives the vco tuning voltage via the charge pump (cp) (confgured in reg 09h ) to the vco subsystem. some of the additional pll subsystem functions include: ? delta sigma confguration ( reg 06h ) ? exact frequency mode (confgured in reg 0ch , reg 03h , and reg 04h ) ? lock detect (ld) confguration ( reg 07h to confgure ld, and reg 0fh to confgure ld_sdo output pin) ? external cen pin used as hardware pll enable pin. cen pin does not affect the vco subsystem. typically, only writes to the divider registers (integer part reg 03h , fractional part reg 04h ) of the pll subsystem are required for HMC832LP6GE output frequency changes. divider registers of the pll subsystem ( reg 03h , and reg 04h ), set the fundamental frequency (1500 mhz to 3000 mhz) of the vco subsystem. output frequencies ranging from 25 mhz to 1500 mhz are generated by tuning to the appropriate fundamental vco frequency (1500 mhz to 3000 mhz) by programming n divider ( reg 03h , and reg 04h ), and programming the output divider (divide by 1/2/4/6.../60/62, programmed in vco_reg 02h ) in the vco subsystem. for detailed frequency tuning information and example, please see 1.5.7 frequency tuning section. 1.2 vco subsystem overview the vco subsystem consists of a capacitor switched step tuned vco and an output stage. in typical operation, the vco subsystem is programmed with the appropriate capacitor switch setting which is executed automatically by the pll subsystem autocal state machine if autocal is enabled ( reg 0ah [11] = 0, see section 1.4.1 vco calibration for more information). the vco tunes to the fundamental frequency (1500 mhz to 3000 mhz), and is locked by the cp output from the pll subsystem. the vco subsystem controls the output stage of the HMC832LP6GE enabling confguration of: ? user defned performance settings ( programmable performance technology ) confgured via vco_ reg 03h [1:0] www.datasheet.net/ datasheet pdf - http://www..co.kr/
19 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz ? vco output divider settings confgured in vco_reg 02h (divide by 2/4/6...60/62 to generate frequencies from 25 mhz to 1500 mhz, or divide by 1 to generate fundamental frequencies between 1500 mhz and 3000 mhz) ? output gain settings ( vco_reg 07h [3:0]) ? output return loss setting ( vco_reg 03h [5]). see figure 24 for more information. ? single-ended or differential output operation ( vco_reg 03h [3:2]) ? mute ( vco_reg 03h [8:7]) 1.3 spi (serial port interface) confguration of pll & vco subsystems the two subsystems (pll subsystem & vco subsystem) have their own register maps as shown in pll register map and vco subsystem register map sections. typically writes to both register maps are required for initialization and frequency tuning operations. as shown in figure 39 , the pll subsystem is connected directly to the spi of the HMC832LP6GE, while the vco subsystem is connected indirectly through the pll subsystem to the HMC832LP6GE spi. as a result, writes to the pll register map are written directly and immediately, while the writes to the vco subsystem register map are written to the pll subsystem reg 05h and forwarded via the internal vco spi (vspi) to the vco subsystem. this is a form of indirect addressing. note that vco subsystem registers are write only and cannot be read. more information is available in 1.3.1 vco serial port interface (vspi) section. 1.3.1 vco serial port interface (vspi) the HMC832LP6GE communicates with the internal vco subsystem via an internal 16-bit vco spi. the internal serial port is used to control the step tuned vco and other vco subsystem functions. note that the internal vco subsystem spi (vspi) runs at the rate of the autocal fsm clock, t fsm , (section 1.4.1.1 ) where the fsm clock frequency cannot be greater than 50 mhz. the vspi clock rate is set by reg 0ah [14:13]. writes to the vcos control registers are handled indirectly, via writes to reg 05h of the HMC832LP6GE. a write to HMC832LP6GE reg 05h causes the internal pll subsystem to forward the packet, msb frst, across its internal serial link to the vco subsystem, where it is interpreted. 1.3.1.1 vspi use of reg05h the packet data written into, reg 05h is sub-parsed by logic at the vco subsystem into the following 3 felds: 1. [2:0] - 3 bits - vco_id, target subsystem address = 000b. 2. [6:3] - 4 bits - vco_regaddr, the internal register address inside the vco subsystem. 3. [15:7] - 9- bits- vco_data, data feld to write into the vco register. for example, to write 0_1111_1110 into register 2 of the vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to reg 05h =0 _1111_1110, 0 010, 0 0 0 b, or equivalently reg 05h =0fe20h. during autocal, the autocal controller writes into the vco register address specifed by the vco_id and vco_regaddr, as stored in reg 05h [2:0] and reg 05h [6:3] respectively. autocal expects these values to be zero ( reg 05h [6:0]=0). if they are not zero ( reg 05h [6:0]0), autocal will not function. to ensure autocal functions it is critical to write reg 05h [6:0]=0 after the last vco subsystem write prior to an output frequency change triggered by a write to reg 03h , or reg 04h . however, it is impossible to write only reg 05h [6:0]=0 (vco_regaddr) without writing reg 05h [15:7] (vco_data). therefore, to ensure that the vco_data ( reg 05h [15:7]) in vco_regaddr 0 is not changed it is required to read the switch settings provided in reg 10h [7:0], and then rewrite them to reg 05h [15:7]. please see an example below. www.datasheet.net/ datasheet pdf - http://www..co.kr/
20 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com first read reg 10h , then write to reg 05h as follows: ? read reg 10h , to obtain vco sub-band settings ? write reg 05h [6:0] = 0 to set the vco address to 0 for following writes ? write the following to set the vco sub-band settings ? reg 05h [15:14] = reg 10h [7:6] ? reg 05h [13] = 1 reserved bit ? reg 05h [12:7] = reg 10h [5:0] changing the vco subsystem confguration ( 3.0 vco subsystem register map ) without following the procedure above will result in failure to lock to the desired frequency. for applications not using the read functionality of the HMC832LP6GE spi, in which reg 10h cannot be read, it is possible to write ? reg 05h = 0h to set reg 05h [6:0] = 0, which also sets vco sub-band setting ( reg 05h [15:7]=0) to zero, effectively programming incorrect vco sub-band settings and causing the HMC832LP6GE to lose lock. ? immediately followed by a write to: ? reg 03h , if in integer mode ? or reg 04h , if in fractional mode. which effectively re-triggers the autocal state machine forcing the HMC832LP6GE to re-lock. this procedure will cause the HMC832LP6GE to lose lock and re-lock after every vco subsystem change. typical output frequency and lock time can be observed in figure 25 and figure 26 , and is typically in the order of 100 s for a phase settling of 10, and is also dependent on loop flter design (loop flter bandwidth and loop flter phase margin). 1.4 vco subsystem the HMC832LP6GE contains a vco subsystem that can be confgured to operate in: ? fundamental frequency (fo) mode (1500 mhz to 3000 mhz). ? divide by n mode, where n = 2,4,6,8...58,60,62 (25 mhz to 1500 mhz). all modes are vco register programmable as shown in figure 40 . one loop flter design can be used for the entire frequency of operation of the HMC832LP6GE. www.datasheet.net/ datasheet pdf - http://www..co.kr/
21 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz figure 40. pll and vco subsystems 1.4.1 vco calibration 1.4.1.1 vco auto-calibration (autocal) the HMC832LP6GE uses a step tuned type vco. a simplifed step tuned vco is shown in figure 41 . a step tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequency of the vco to be adjusted or stepped by switching in/out vco tank capacitors. a step tuned vco allows the user to center the vco on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the HMC832LP6GEs charge pump. this enables the pll charge pump to tune the vco over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). the vco switches are normally controlled automatically by the HMC832LP6GE using the auto-calibration feature. the auto-calibration feature is implemented in the internal state machine. it manages the selection of the vco sub-band (capacitor selection) when a new frequency is programmed. the vco switches may also be controlled directly via register reg 05h for testing or for other special purpose operation. other control bits specifc to the vco are also sent via reg 05h . www.datasheet.net/ datasheet pdf - http://www..co.kr/
22 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 41. simplifed step tuned vco to use a step tuned vco in a closed loop, the vco must be calibrated such that the HMC832LP6GE knows which switch position on the vco is optimum for the desired output frequency. the HMC832LP6GE supports auto-calibration (autocal) of the step tuned vco. the autocal fxes the vco tuning voltage at the optimum mid-point of the charge pump output, then measures the free running vco frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency. this procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor. a typical tuning curve for a step tuned vco is shown in figure 42 . note how the tuning voltage stays in a narrow range over a wide range of output frequencies. 0 0.5 1 1.5 2 2.5 3 3.5 tune voltage after calibration (v) vco frequency(mhz) fmin fmax 1500 3000 figure 42. typical vco tuning voltage after calibration the calibration is normally run automatically once for every change of frequency. this ensures optimum selection of vco switch settings vs. time and temperature. the user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the autocal routine. the accuracy required in the calibration affects the amount of time required to tune the vco. the calibration routine searches for the best step setting that locks the vco at the current programmed frequency, and ensures that the vco will stay locked and perform well over its full temperature range without additional calibration, regardless of the temperature that the vco was calibrated at. auto-calibration can also be disabled allowing manual vco tuning. refer to section 1.4.1.6 for a description of manual tuning www.datasheet.net/ datasheet pdf - http://www..co.kr/
23 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 1.4.1.2.2 autocal use of reg05h autocal transfers switch control data to the vco subsystem via reg 05h . the address of the vco subsystem in reg 05h is not altered by the autocal routine. the address and id of the vco subsystem in reg 05h must be set to the correct value before autocal is executed. for more information see section 1.3.1 . 1.4.1.3.3 auto-relock on lock detect failure it is possible by setting reg 07h [13] to have the vco subsystem automatically re-run the calibration routine and re-lock itself if lock detect indicates an unlocked condition for any reason. with this option the system will attempt to re-lock only once. 1.4.1.4.4 vco autocal on frequency change assuming reg 0ah [11]= 0 , the vco calibration starts automatically whenever a frequency change is requested. if it is desired to rerun the autocal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the autocal routine will execute again without changing fnal frequency. 1.4.1.5.5 vco autocal time & accuracy the vco frequency is counted for t mmt , the period of a single autocal measurement cycle. t mmt = t xtal r 2 n (eq 1) n is set by reg 0ah [2:0] and results in measurement periods which are multiples of the pd period, t xtal r . r is the reference path division ratio currently in use, reg 02h t xtal is the period of the external reference (crystal) oscillator. the vco autocal counter will, on average, expect to register n counts, rounded down (foor) to the nearest integer, every pd cycle. n is the ratio of the target vco frequency, f vco , to the frequency of the pd, f pd , where n can be any rational number supported by the n divider. n is set by the integer ( n int = reg 03h ) and fractional ( n frac = reg 04h ) register contents n = n int + n frac / 2 24 (eq 2) the autocal state machine and the data transfers to the internal vco subsystem spi (vspi) run at the rate of the fsm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. t fsm = t xtal 2 m (eq 3) m is 0, 2, 4 or 5 as determined by reg 0ah [14:13] the expected number of vco counts, v, is given by v = foor (n 2 n ) (eq 4) the nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r) (eq 5) where the worst case measurement error, f err , is: f err f pd / 2 n + 1 (eq 6) www.datasheet.net/ datasheet pdf - http://www..co.kr/
24 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 43. vco calibration a 5-bit step tuned vco, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 vspi data transfers of 20 clock cycles each. total calibration time, worst case, is given by: t cal = k128t fsm + 6t pd 2 n + 7 20t fsm (eq 7) or equivalently t cal = t xtal (6r 2 n + (140+(3 128)) 2 m ) (eq 8) for guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8 th the frequency step caused by a vco sub-band switch change. better resolution settings will show no improvement. 1.4.1.5.1.1 vco autocal example the vco subsystem must satisfy the maximum f pd limited by the two following conditions: a. n 16 (f int ), n 20.0 (f frac ), where n = f vco/ f pd b. f pd 100 mhz suppose the vco subsystem output frequency is to operate at 2.01 ghz. our example crystal frequency is f xtal = 50 mhz, r=1, and m=0 ( figure 43 ) , hence t fsm = 20 ns (50 mhz). note, when using autocal, the maximum autocal finite state machine (fsm) clock cannot exceed 50 mhz (see reg 0ah [14:13] ). the fsm clock does not affect the accuracy of the measurement, it only affects the time to produce the result. this same clock is used to clock the 16 bit vco serial port. if time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. using an input crystal of 50 mhz (r=1 and fpd=50 mhz) the times and accuracies for calibration using (eq 6) and (eq 8) are shown in table 2 . where minimal tuning time is 1/8 th of the vco band spacing. across all vcos, a measurement resolution better than 800 khz will produce correct results. setting m = 0, n = 5, provides 781 khz of resolution and adds 8.6 s of autocal time to a normal frequency hop. once the autocal sets the fnal switch value, 8.64 s after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. hence as shown in this example that autocal typically adds about 8.6 s to the normal time to achieve frequency lock. hence, autocal should be used for all but the most extreme frequency hopping requirements. www.datasheet.net/ datasheet pdf - http://www..co.kr/
25 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz table 2. autocal example with f xtal = 50 mhz, r = 1, m = 0 control value reg0ah[2:0] n 2 n t mmt (s) t cal (s) f err max 0 0 1 0.02 4.92 25 mhz 1 1 2 0.04 5.04 12.5 mhz 2 2 4 0.08 5.28 6.25 mhz 3 3 8 0.16 5.76 3.125 mhz 4 5 32 0.64 8.64 781 khz 5 6 64 1.28 12.48 390 khz 6 7 128 2.56 20.16 195 khz 7 8 256 5.12 35.52 98 khz 1.4.1.6 manual vco calibration for fast frequency hopping if it is desirable to switch frequencies quickly it is possible to eliminate the autocal time by calibrating the vco in advance and storing the switch number vs frequency information in the host. this can be done by initially locking the HMC832LP6GE on each desired frequency using autocal, then reading, and storing the selected vco switch settings. the vco switch settings are available in reg 10h [7:0] after every autocal operation. the host must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers when autocal is disabled. hence frequency changes with manual control and autocal disabled, requires a minimum of two serial port transfers to the pll, once to set the vco switches, and once to set the pll frequency. if autocal is disabled reg 0ah [11]=1, the vco will update its registers with the value written via reg 05h immediately. the vco internal transfer requires 16 vsck clock cycles after the completion of a write to reg 05h . vsck and the autocal controller clock are equal to the input reference divided by 0, 4, 16 or 32 as controlled by reg 0ah [14:13]. 1.4.2 registers required for frequency changes in fractional mode a large change of frequency, in fractional mode ( reg 06h [11]=1), may require main serial port writes to: 1. the integer register intg, reg 03h (only required if the integer part changes) 2. the vco spi register, reg 05h ? only required for manual control of vco if reg 0ah [11] =1 (autocal disabled) ? required to change the vco output divider value if needed ( vco_reg 02h ), please see figure 40 for more information. 3. the fractional register, reg 04h . the fractional register write triggers autocal if reg 0ah [11]=0, and is loaded into the modulator automatically after autocal runs. if autocal is disabled, reg 0ah [11] =1, the fractional frequency change is loaded into the modulator immediately when the register is written with no adjustment to the vco. small steps in frequency in fractional mode, with autocal enabled ( reg 0ah [11]=0), usually only require a single write to the fractional register. worst case, 3 main serial port transfers to the HMC832LP6GE could be required to change frequencies in fractional mode. if the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. in all cases, in fractional mode, it is necessary to write to the fractional register reg 04h for frequency changes. www.datasheet.net/ datasheet pdf - http://www..co.kr/
26 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 1.4.3 registers required for frequency changes in integer mode a change of frequency, in integer mode ( reg 06h [11]=0), requires main serial port writes to: 1. vco spi register, reg 05h ? only required for manual control of vco if reg 0ah [11]=1 (autocal disabled) ? required to change the vco output divider value if needed ( vco_reg 02h ) 2. the integer register reg 03h . ? in integer mode, an integer register write triggers autocal if reg 0ah [11]=0, and is loaded into the prescaler automatically after autocal runs. if autocal is disabled, reg 0ah [11]=1, the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the vco. normally changes to the integer register cause large steps in the vco frequency, hence the vco switch settings must be adjusted. autocal enabled is the recommended method for integer mode frequency changes. if autocal is disabled ( reg 0ah [11]=1), a priori knowledge of the correct vco switch setting and the corresponding adjustment to the vco is required before executing the integer frequency change. 1.4.4 vco output mute function the HMC832LP6GE features an intelligent output mute function with the capability to disable the vco output while maintaining the pll and vco subsystems fully functional. the mute function is automatically controlled by the HMC832LP6GE, and provides a number of mute control options including: 1. automatically mute the outputs during vco calibration that occurs during output frequency changes. this mode can be useful in eliminating any out of band emissions during frequency changes, and ensuring that the system emits only desired frequencies. it is enabled by writing vco_reg 03h [8:7] = 1d. 2. always mute ( vco_reg 03h [8:7] = 3d). this mode is used for manual mute control. typical isolation when the HMC832LP6GE is muted is always better than 50 db, and is ~ 40 db better than disabling the individual outputs of the HMC832LP6GE via vco_reg 03h [3:2] as shown in figure 35 . please refer to figure 40 for more information. also note that the vco subsystem registers are not directly accessible. they are written to the vco subsystem via pll reg 05h . more information about vco subsystem spi in section 1.3.1 . 1.4.5 vco built in test with autocal the frequency limits of the vco can be measured using the bist features of the autocal machine. this is done by setting reg 0ah [10]=1 which freezes the vco switches in one position. vco switches may then be written manually, with the varactor biased at the nominal mid-rail voltage used for autocal. for example to measure the vco maximum frequency use switch 0, written to the vco subsystem via reg 05h =[000000001 0000 vcoid]. where vcoid = 000b. if autocal is enabled, ( reg 0ah [11] = 0), and a new frequency is written, autocal will run. the vco frequency error relative to the command frequency will be measured and results written to re g 11h [19:0] where re g 11h [19] is the sign bit. the result will be written in terms of vco count error (eq 4) . for example if the expected vco is 2 ghz, reference is 50 mhz, and n is 6, we expect to measure 2000/(50/2 6 )=2560 counts. if we measure a difference of -5 counts in re g 11h , then it means we actually measured 2555 counts. hence the actual frequency of the vco is 5/2560 low, or 1.99609375 ghz, 1 count ~ 781 khz. www.datasheet.net/ datasheet pdf - http://www..co.kr/
27 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 1.5 pll subsystem 1.5.1 charge pump (cp) & phase detector (pd) the phase detector (pd) has two inputs, one from the reference path divider and one from the rf path divider. when in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. we refer to the frequency of operation of the pd as f pd . most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the pd, f pd . f pd is also referred to as the comparison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians (360) of input phase difference. 1.5.1.1 charge pump a simplifed diagram of the charge pump is shown in figure 44 . the cp consists of 4 programmable current sources, two controlling the cp gain (up gain reg 09h [13:7], and down gain reg 09h [6:0]) and two controlling the cp offset, where the magnitude of the offset is set by reg 09h [20:14], and the direction is selected by reg 09h [21]=1 for up and reg 09h [22]=1 for down offset. cp gain is used at all times, while cp offset is only recommended for fractional mode of operation. typically the cp up and down gain settings are set to the same value ( reg 09h [13:7] = reg 09h [6:0]). figure 44. charge pump gain & offset control 1.5.1.2.2 charge pump gain charge pump up and down gains are set by reg 09h [6:0] and reg 09h [13:7] respectively. the current gain of the pump in amps/radian is equal to the gain setting of this register divided by 2. typical cp gain setting is set to 2 to 2.5 ma, however lower values can also be used. values < 1 ma may result in degraded phase noise performance. for example, if both reg 09h [13:7] and reg 09h [6:0] are set to 50d the output current of each pump will be 1 ma and the phase frequency detector gain k p = 1 ma/2 radians, or 159 a/rad. see section 1.5.1 for more information. 1.5.1.3.3 charge pump phase offset in integer mode, the phase detector operates with zero offset. the divided reference signal and the divided vco signal arrive at the phase detector inputs at the same time. integer mode does not require any cp www.datasheet.net/ datasheet pdf - http://www..co.kr/
28 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com offset current. when operating in integer mode simply disable cp offset in both directions (up and down), by writing reg 09h [22:21] = 00b and set the cp offset magnitude to zero by writing reg 09h [20:14]= 0. in fractional mode cp linearity is of paramount importance. any non-linearity degrades phase noise and spurious performance. in fractional mode, these non-linearities are eliminated by operating the pd with an average phase offset, either positive or negative (either the reference or the vco edge always arrives frst at the pd ie. leads). a programmable cp offset current source is used to add dc current to the loop flter and create the desired phase offset. positive current causes the vco to lead, negative current causes the reference to lead. the cp offset is controlled via reg 09h . the phase offset is scaled from 0 degrees, that is the reference and the vco path arrive in phase, to 360 degrees, where they arrive a full cycle late. the specifc level of charge pump offset current reg 09h [20:14] is provided in (eq 9) . it is also plotted in figure 45 vs. pd frequency for typical cp gain currents. ( ) 9 4.3 10 ,0.25 required cp offset min pd cp cp fi i ? ?? ?? ?? = where: f pd : comparison frequency of the phase detector (hz) i cp : is the full scale current setting (a) of the switching charge pump (set in reg 09h [6:0] reg 09h [13:7]) (eq 9) figure 45. 0 100 200 300 400 500 600 700 0 20 40 60 80 100 recommended offset current (ua) phase detector frequency (mhz) cp current = 2.5 ma cp current = 2 ma cp current = 1 ma recommended cp offset current vs pd frequency for typical cp gain currents. calculated using (eq 9) the required cp offset current should never exceed 25 % of the programmed cp current. it is recommended to enable the up offset and disable the down offset by writing reg 09h [22:21] = 01b. operation with cp offset infuences the required confguration of the lock detect function. refer to the description of lock detect function in section 1.5.5 . 1.5.1.4 phase detector functions phase detector register reg 0bh allows manual access to control special phase detector features. setting reg 0bh [5] = 0, masks the pd up output, which prevents the charge pump from pumping up.` setting ( reg 0bh [6]) = 0 , masks the pd down output, which prevents the charge pump from pumping down. clearing both reg 0bh [5] and reg 0bh [6] tri-states the charge pump while leaving all other functions operating internally. www.datasheet.net/ datasheet pdf - http://www..co.kr/
29 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz pd force up reg 0bh [9] = 1 and pd force dn reg 0bh [10] = 1 allows the charge pump to be forced up or down respectively. this will force the vco to the ends to the tuning range which can be useful in test of the vco. 1.5.2 reference input stage figure 46. reference path input stage the reference buffer provides the path from an external reference source (generally crystal based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation controlled by reg 08h [21]. high gain ( reg 08h [21] = 0), recommended below 200 mhz, and high frequency ( reg 08h [21] = 1), for 200 to 350 mhz operation. the buffer is internally dc biased, with 100 internal termination. for 50 match, an external 100 resistor to ground should be added, followed by an ac coupling capacitor (impedance < 1 ), then to the xrefp pin of the part. at low frequencies, a relatively square reference is recommended to keep the input slew rate high. at higher frequencies, a square or sinusoid can be used. the following table shows the recommended operating regions for different reference frequencies. if operating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. table 3. reference sensitivity table square input sinusoidal input reference input frequency (mhz) slew > 0.5v/ns recommended swing (vpp) recommended power range (dbm) recommended min max recommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1. 2 2.5 yes 3 8 input referred phase noise of the pll when operating at 50 mhz is between -148 and -150 dbc/hz at 10 khz offset depending upon the mode of operation. the input reference signal should be 10 db better than this foor to avoid deg radation of the pll noise contribution. it should be noted that such low levels are only necessary if the pll is the dominant noise contributor and these levels are required for the system goals. www.datasheet.net/ datasheet pdf - http://www..co.kr/
30 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 1.5.3 reference path r divider the reference path r divider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled via reg 02h . 1.5.4 rf path n divider the main rf path divider is capable of average divide ratios between 2 19 -5 (524,283) and 20 in fractional mode, and 2 19 -1 (524,287) to 16 in integer mode. the vco frequency range divided by the minimum n divider value will place practical restrictions on the maximum usable pd frequency. for example a vco operating at 1.5 ghz in fractional mode with a minimum n divider value of 20 will have a maximum pd frequency of 75 mhz. 1.5.5 lock detect the lock detect (ld) function indicates that the HMC832LP6GE is indeed generating the desired frequency. it is enabled by writing reg 07h [3]=1. the HMC832LP6GE provides ld indicator in one of two ways: ? as an output available on the ld_sdo pin of the HMC832LP6GE, (confguration is required to use the ld_sdo pin for ld purpose, for more information please see 1.10 serial port and 1.5.5.3 confguring ld_sdo pin for ld output section). ? or reading from reg 12h [1], where reg 12h [1] = 1 indicates locked and reg 12h [1] = 0 indicates an unlocked condition. the ld circuit expects the divided vco edge and the divided reference edge to appear at the pd within a user specifed time period (window), repeatedly. either signal may arrive frst, only the difference in arrival times is signifcant. the arrival of the two edges within the designated window increments an internal counter. once the count reaches and exceeds a user specifed value ( reg 07h [2:0]) the HMC832LP6GE declares lock. failure in registering the two edges in any one window resets the counter and immediately declares an un-locked condition. lock is deemed to be reestablished once the counter reaches the user specifed value ( reg 07h [2:0]) again. the HMC832LP6GE supports two lock detect modes: ? analog ld, that only supports a fxed window size of 10 ns. analog ld mode is selected by writing reg 07h [6] = 0. ? digital ld, that supports a user confgurable window size, programmed in reg 07h [11:7]. digital ld is selected by writing reg 07h [6] = 1. 1.5.5.1 lock detect confguration optimal spectral performance in fractional mode requires cp current and cp offset current confguration discussed in detail in section 1.5.1 charge pump (cp) & phase detector (pd) . these settings in reg 09h impact the required ld window size in fractional mode of operation. to function, the required lock detect window size is provided by (eq 10) . www.datasheet.net/ datasheet pdf - http://www..co.kr/
31 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz ( ) ( ) ( ) ( ) ( ) ( ) ( ) 9 1 2.66 10 sec ld window seconds in fractional mode 2 1 ld window seconds in integer mode 2 cp offset pd cp pd pd ia f hz i a f hz f ? ?? ?? + + ?? ?? = = where: f pd : is the comparison frequency of the phase detector i cp offset : is the charge pump offset current reg 09h [20:14] i cp : is the full scale current setting of the switching charge pump reg 09h [6:0], or reg 09h [13:7] (eq 10) if the result provided by (eq 10) is equal to 10 ns analog ld can be used ( reg 07h [6] = 0). otherwise digital ld is necessary reg 07h [6] = 1. table 4 provides the required reg 07h settings to appropriately program the digital ld window size. from table 4 , simply select the closest value in the digital ld window size columns to the one calculated in (eq 10) and program reg 07h [11:10] and reg 07h [9:7] accordingly. table 4. typical digital lock detect window ld timer speed reg07[11:10] digital lock detect window size nominal value (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 7.1 9.2 13.3 22 38 72 138 272 slowest 11 7.6 10.2 15.4 26 47 88 172 338 ld timer divide setting reg07[9:7] 000 001 010 011 100 101 110 111 1.5.5.2 digital window confguration example assuming, fractional mode, with a 50 mhz pd and ? charge pump gain of 2 ma ( reg 09h [13:7] = 64h, reg 09h [6:0] = 64h), ? up offset ( reg 09h [22:21] = 01b) ? and offset current magnitude of +400 a ( reg 09h [20:14] = 50h) applying (eq 10) , the required ld window size is: ( ) ( ) ( ) ( ) ( ) ( ) 3 9 63 6 0.4 10 1 2.66 10 sec 50 10 2 10 50 10 ld window seconds 13.33 nsec 2 xa hz x a hz ? ? ? ?? ?? + + ?? ?? = = (eq 11) locating the table 4 value that is closest to the (eq 11) result, in this case 13.3 13.33. to set the digital ld window size, simply program reg 07h [11:10] = 10b and reg 07h [9:7] = 010b according to table 4 . there is always a good solution for the lock detect window for a given operating point. the user should understand however that one solution does not ft all operating points. as observed from (eq 10) , if charge pump offset or pd frequency are changed signifcantly then the lock detect window may need to be adjusted. 1.5.5.3 confguring ld_sdo pin for ld output setting reg 0fh [7]=1 and reg 0fh [4:0]=1 will display the lock detect flag on ld_sdo pin of the HMC832LP6GE. if locked, ld_sdo will be high. as the name suggests, ld_sdo pin is multiplexed between ld and sdo (serial data out) signals. hence ld is available on the ld_sdo pin at all times www.datasheet.net/ datasheet pdf - http://www..co.kr/
32 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com except when a serial port read is requested, in which case the pin reverts temporarily to the serial data out pin, and returns to the lock detect flag after the read is completed. ld can be made available on ld_sdo pin at all times by writing reg 0fh [6] = 1. in that case the HMC832LP6GE will not provide any read-back functionality because the sdo signal is not available. 1.5.6 cycle slip prevention (csp) when changing vco frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two pd inputs are different, and the phase difference of the two inputs at the pd varies rapidly over a range much greater than 2 radians. since the gain of the pd varies linearly with phase up to 2, the gain of a conventional pd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. the output current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. the charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency actually reverse temporarily during locking. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle slipping increases the time to lock to a value greater than that predicted by normal small signal laplace analysis. the HMC832LP6GE pd features an ability to reduce cycle slipping during acquisition. the cycle slip preven tion (csp) feature increases the pd gain during large phase errors. the specifc phase error that triggers the momentary increase in pd gain is set via reg 0bh [8:7] 1.5.7 frequency tuning HMC832LP6GE vco subsystem always operates in fundamental frequency of operation (1500 mhz to 3000 mhz). the HMC832LP6GE generates frequencies below its fundamental frequency (25 mhz to 1500 mhz) by tuning to the appropriate fundamental frequency and selecting the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_reg 02h [5:0]. the HMC832LP6GE automatically controls frequency tuning in the fundamental band of operation, for more information see 1.4.1.1 vco auto-calibration (autocal) . to tune to frequencies below the fundamental frequency range (<1500 mhz) it is required to tune the HMC832LP6GE to the appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_reg 02h [5:0]. 1.5 .7.1 integer mode the HMC832LP6GE is capable of operating in integer mode. for integer mode set the following registers a. disable the fractional modulator, reg 06h [11]= 0 b. bypass the modulator circuit, reg 06h [7]=1 in integer mode the vco step size is fxed to that of the pd frequency. integer mode typically has 3 db lower phase noise than fractional mode for a given pd operating frequency. integer mode, however, often requires a lower pd frequency to meet step size requirements. the fractional mode advantage is that higher pd frequencies can be used, hence lower phase noise can often be realized in fractional mode. charge pump offset should be disabled in integer mode. 1.5.7.2.2 integer frequency tuning in integer mode the digital ? modulator is shut off and the n divider ( reg 03h ) may be programmed to any integer value in the range 16 to 2 19 -1. to run in integer mode confgure reg 06h as described, then program the integer portion of the frequency as explained by (eq 12) , ignoring the fractional part. a. disable the fractional modulator, reg 06h [11] = 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
33 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz b. bypass the delta-sigma modulator reg 06h [7] = 1 c. to tune to frequencies (<1500 mhz), select the appropriate output divider value vco_reg 02h [5:0]. writing to vco subsystem registers ( vco_reg 02h [5:0] and vco_reg 03h [0] in this case ) is accomplished indirectly through pll register 5 ( reg 05h ). more information on communicating with the vco subsystem through pll reg 05h is available in 1.3.1 vco serial port interface (vspi) section. 1.5 .7.3 fractional mode the HMC832LP6GE is placed in fractional mode by setting the following registers: a. enable the fractional modulator, reg 06h [11]=1 b. connect the delta sigma modulator in circuit, reg 06h [7]=0 1.5.7.4.4 fractional frequency tuning this is a generic example, with the goal of explaining how to program the output frequency. actual variables are dependant upon the reference in use. the HMC832LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference. the frequency of the HMC832LP6GE, f vco , is given by f vco = ( n int + n frac ) = f int + f frac f xtal r (eq 12) f out = f vco / k (eq 13) where: f out is the output frequency after any potential dividers. k is 1 for fundamental, or k = 2,4,6,58,60,62 depending on the selected output divider value ( reg 05h [5:0] indirectly to vco_reg 02h [5:0]) n int is the integer division ratio, reg 03h , an integer number between 20 and 524,284 n frac is the fractional part, from 0.0 to 0.99999...,n frac = reg 04h /2 24 r is the reference path division ratio, reg 02h f xtal is the frequency of the reference oscillator input f pd is the pd operating frequency, f xtal /r as an example: f out 1402.5 mhz k 2 f vco 2,805 mhz f xtal = 50 mhz r = 1 f pd = 50 mhz n int = 56 n frac = 0.1 reg 04h = round(0.1 x 2 24 ) = round(1677721.6) = 1677722 www.datasheet.net/ datasheet pdf - http://www..co.kr/
34 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com f vco = ( 56 + ) = 2805 mhz + 1.192 hz error 1677722 2 24 50e6 1 (eq 14) f out = = 1402.5 mhz + 0.596 hz error f vco 2 (eq 15) in this example the output frequency of 1402.5 mhz is achieved by programming the 19-bit binary value of 56d = 38h into intg_reg in reg 03h , and the 24-bit binary value of 1677722d = 19999ah into frac_reg in reg 04h . the 0.596 hz quantization error can be eliminated using the exact frequency mode if required. in this example the output fundamental is divided by 2. specifc control of the output divider is required. see section 3.0 and description for more details. 1.5.7.5.5 exact frequency tuning due to quantization effects, the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example, a 24 bit fractional modulator has frequency resolution set by the phase detector (pd ) comparison rate divided by 2 24 . the value 2 24 in the denominator is sometimes referred to as the modulus. hittite plls use a fxed modulus which is a binary number. in some types of fractional plls the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). for this reason hittite plls use a large fxed modulus. normally, the step size is set by the size of the fxed modulus. in the case of a 50 mhz pd rate, a modulus of 2 24 would result in a 2.98 hz step resolution, or 0.0596 ppm. in some applications it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tol erated. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary (eg. n = 50.0,50.5,50.25,50.75 etc.). unfortunately, some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. at f pd = 50 mhz this translates to 1.2 hz error. hittites exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to f pd /10 in reg 0ch to 10 (in this example). more generally, this feature can be used whenever the desired frequency, f vco , can be exactly represented on a step plan where there are an integer number of steps (<2 14 ) across integer-n boundaries. mathematically, this situation is satisfed if: gcd gcd gcd 1 14 mod 0 where gcd( , ) 2 pd pd vcok vco f f f f f f and f ?? ?? ?? ?? ?? ?? ?? = = (eq 16) where: gcd stands for greatest common divisor f n = maximum integer boundary frequency < f vco1 f pd = frequency of the phase detector and f vcok are the channel step frequencies where 0 < k < 2 24 -1, as shown in figure 47 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
35 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz figure 47. exact frequency tuning some fractional plls are able to achieve this by adjusting (shortening) the length of the phase accumulator (the denominator or the modulus of the delta-sigma modulator) so that the delta-sigma modulator phase accumulator repeats at an exact period related to the interval frequency ( f vcok - f vco(k-1) ) in figure 47 . consequently, the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok - f vco(k-1) . for example, in some applications, these intervals might represent the spacing between radio channels, and the spurious would occur at multiples of the channel spacing. the hittite method on the other hand is able to generate exact frequencies between adjacent integer-n boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector comparison rate, which allows hittite plls to maintain excellent phase noise and spurious performance in the exact frequency mode. 1.5.7.6.6 using hittite exact frequency mode if the constraint in (eq 16) is satisfed, HMC832LP6GE is able to generate signals with zero frequency error at the desired vco frequency. exact frequency mode may be re-confgured for each target frequency, or be set-up for a fxed f gcd which applies to all channels. 1.5.7.6.1.1 confguring exact frequency mode for a particular frequency 1. calculate and program the integer register setting reg 03h = n int = foor( f vco / f pd ), where the foor function is the rounding down to the nearest integer. then the integer boundary frequency f n = n int ? f pd 2. calculate and program the exact frequency register value reg 0ch = f pd / f gcd , where f gcd = gcd( f vco , f pd ) 3. calculate and program the fractional register setting reg 04h ( ) 24 2 ceil n vco frac pd ff n f ?? ?? ?? ?? ?? ? = = , where ceil is the ceiling function meaning round up to the nearest integer. example: to confgure the HMC832LP6GE for exact frequency mode at f vco = 2800.2 mhz where phase detector (pd) rate f pd = 61.44 mhz proceed as follows: check (eq 16) to confrm that the exact frequency mode for this f vco is possible. www.datasheet.net/ datasheet pdf - http://www..co.kr/
36 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com ( ) gcd gcd 14 6 66 3 gcd 14 gcd( , ) 2 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 pd pd vco f f f f and f f ?? ?? ?? ?? = = => = since (eq 16) is satisfed, the HMC832LP6GE can be confgured for exact frequency mode at f vco = 2800.2 mhz as follows: 1. n int = reg 03h = 6 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) 66 66 61.44 10 61.44 10 512 200 120000 gcd , gcd 2800.2 10 ,61.44 10 pd pd vco f dh ff = = = = 3. to program reg 04h , the closest integer-n boundary frequency f n that is less than the desired vco frequency f vco must be calculated. f n = f pd ? n int . using the current example: ( ) ( ) 6 24 6 6 24 6 45 61.44 10 2764.8 . 2 2800.2 10 2764.8 10 2 then reg04h 9666560 938000 61.44 10 int n pd n vco pd n f f mhz ff ceil ceil d h f ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = = = ? ? = = = = 1.5.7.7.7 hittite exact frequency channel mode if it is desirable to have multiple, equally spaced, exact frequency channels that fall within the same interval (ie. f n f vcok < f n+1 ) where f vcok is shown in figure 47 and 1 k 2 14 , it is possible to maintain the same integer-n ( reg 03h ) and exact frequency register ( reg 0ch ) settings and only update the fractional register ( reg 04h ) setting. the exact frequency channel mode is possible if (eq 16) is satisfed for at least two equally spaced adjacent frequency channels, i.e. the channel step size. to confgure the HMC832LP6GE for exact frequency channel mode, initially and only at the beginning, integer ( reg 03h ) and exact frequency ( reg 0ch ) registers need to be programmed for the smallest f vco frequency ( f vco1 in figure 47 ), as follows: 1. calculate and program the integer register setting reg 03h = n int = foor( f vco1 / f pd ), where f vco1 is shown in figure 47 and corresponds to minimum channel vco frequency. then the lower integer boundary frequency is given by f n = n int ? f pd . 2. calculate and program the exact frequency register value reg 0ch = f pd / f gcd, where f gcd = gcd(( f vcok+1 - f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing and the pd frequency (( f vcok+1 - f vcok ) and f pd ). then, to switch between various equally spaced intervals (channels) only the fractional register ( reg 04h ) needs to be programmed to the desired vco channel frequency f vcok in the following manner: reg 04h = ( ) 24 2 ceil n vcok frac pd ff n f ?? ?? ?? ?? ?? ? = where f n = foor( f vco1 / f pd ), and f vco1 , as shown in figure 47 , represents the smallest channel vco frequency that is greater than f n . example: to confgure the HMC832LP6GE for exact frequency mode for equally spaced intervals of 100 khz where frst channel (channel 1) = f vco1 = 2800.200 mhz and phase detector (pd) rate f pd = 61.44 mhz proceed as follows: first check that the exact frequency mode for this f vco1 = 2800.2 mhz (channel 1) and f vco2 = 2800.2 mhz + 100 khz = 2800.3 mhz (channel 2) is possible. www.datasheet.net/ datasheet pdf - http://www..co.kr/
37 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz ( ) ( ) gcd1 gcd1 gcd 2 gcd 2 12 14 14 6 66 3 gcd1 14 6 6 63 gcd 2 14 gcd( , ) gcd( , ) 22 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 61.44 10 gcd 2800.3 10 ,61.44 10 20 10 3750 2 pd pd pd pd vco vco ff f f f and f and f f f and f f f ?? ?? ?? ?? ?? ?? ?? ?? = = = => = = => = if (eq 16) is satisfed for at least two of the equally spaced interval (channel) frequencies f vco1 ,f vco2 ,f vco3 ,... f vcon , as it is above, hittite exact frequency channel mode is possible for all desired channel frequencies, and can be confgured as follows: 1. reg 03h = 6 1 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) ( ) 66 36 1 61.44 10 61.44 10 3072 00 20000 gcd 100 10 ,61.44 10 gcd , pd pd vcok vcok f dc h f ff + = = = = ? where ( f vcok+1 - f vcok ) is the desired channel spacing (100 khz in this example). 3. to program reg 04h the closest integer-n boundary frequency f n that is less than the smallest channel vco frequency f vco1 must be calculated. f n = foor( f vco1 / f pd ). using the current example: 6 6 6 2800.2 10 45 61.44 10 2764.8 61.44 10 n pd f f floor mhz ?? ?? ?? ?? = = = then reg 04h ( ) ( ) 24 1 1 24 6 6 6 2 for channel 1 where 2800.2 2 2800.2 10 2764.8 10 9666560 938000 61.44 10 n vco vco pd ff ceil f mhz f ceil d h ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? = = ? = = = 4. to change from channel 1 ( f vco1 = 2800.2 mhz) to channel 2 ( f vco2 = 2800.3 mhz), only reg 04h needs to be programmed, as long as all of the desired exact frequencies f vcok ( figure 47 ) fall between the same integer-n boundaries ( f n < f vcok < f n+1 ). in that case reg 04h = ( ) 24 6 6 6 2 2800.3 10 2764.8 10 9693867 93 61.44 10 ceil d eaabh ?? ?? ?? ?? ?? ?? ? = = , and so on. 1.5.8 seed register the start phase of the fractional modulator digital phase accumulator (dpa) may be set to one of four possible default values via the seed register reg 06h [1:0]. the HMC832LP6GE will automatically reload the start phase (seed value) into the dpa every time a new fractional frequency is selected. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. for most cases a random, or non zero, non-binary start seed is recommended ( reg 06h [1:0] =2 ). 1.6 soft reset & power-on reset the HMC832LP6GE features a hardware power on reset (por). all chip registers will be reset to default states approximately 250 s after power up. the pll subsystem spi registers may also be soft reset by an spi write to register reg 00h . note that the soft reset does not clear the spi mode of operation referred to in section 1.10 . it should be noted that the vco subsystem is not affected by the pll soft reset, the vco subsystem registers can only be reset by removing the power supply. www.datasheet.net/ datasheet pdf - http://www..co.kr/
38 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com note: if external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( reg 00h [5]=1) immediately after power up, before any other spi activity. this will ensure starting from a known state. 1.7 power down mode note that the vco subsystem is not affected by the cen or soft reset. hence device power down is a two step process. first power down the vco by writing 0 to vco register 1 via reg 05h and then power down the pll by pulling cen pin (pin 17) low (assuming no spi overrides ( reg 01h [0]=1)). this will result in all analog functions and internal clocks disabled. current consumption will typically drop below 10 a in power down state. the serial port will still respond to normal communication in power down mode. it is possible to ignore the cen pin, by setting reg 01h [0]=0. control of power down mode then comes from the serial port register reg 01h [1]. it is also possible to leave various blocks on when in power down (see reg 01h ) , including: a. internal bias reference sources reg 01h [2] b. pd block reg 01h [3] c. cp block reg 01h [4] d. reference path buffer reg 01h [5] e. vco path buffer reg 01h [6] f. digital i/o test pads reg 01h [7] to mute the output but leave the pll and vco locked please refer to 1.4.4 section. 1.8 general purpose output (gpo) pin the pll shares the ld_sdo (lock-detect/serial data out) pin to perform various functions. while the pin is most commonly used to read back registers from chip via the spi, it is also capable of exporting a variety of signals and real time test waveforms (including lock detect). it is driven by a tri-state cmos driver with ~200 rout. it has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. in its default confguration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed spi reads. this allows it to share the output with other devices on the same bus. the pin driver is enabled if the chip is addressed - ie. the last 3 bits of spi cycle = 000b before the rising edge of sen. if sen rises before sck has clocked in an invalid (non-zero) chip -address, the HMC832LP6GE will start to drive the bus. to monitor any of the gpo signals, including lock detect, set reg 0fh [7] = 1 to keep the sdo driver always on. this stops the ldo driver from tri-stating and means that the sdo line cannot be shared with other devices. the HMC832LP6GE will naturally switch away from the gpo data and export the sdo during an spi read. to prevent this automatic data selection, and always select the gpo signal, set prevent automux of sdo ( reg 0fh [6] = 1). the phase noise performance at this output is poor and uncharacterized. also, the gpo output should not be toggling during normal operation because it may degrade the spectral performance. note that there are additional controls available, which may be helpful if sharing the bus with other devices: ? to disable the driver completely, set reg 08h [5] = 0 (it takes precedence over all else). ? to disable either the pull-up or pull-down sections of the driver, reg 0fh [8] = 1 or reg 0fh [9] = 1 respectively. example scenarios: ? drive sdo during reads, tri-state otherwise (to allow bus-sharing) ? no action required. www.datasheet.net/ datasheet pdf - http://www..co.kr/
39 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz ? drive sdo during reads, lock detect otherwise ? set gpo select reg 0fh [4:0] = 00001b (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1) ? always drive lock detect ? set prevent automux of sdo reg 0fh [6] = 1 ? set gpo select reg 0fh [4:0]= 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1)) the signals available on the gpo are selected by changing gpo select, reg 0fh [4:0]. 1.9 chip identifcation pll subsystem version information may be read by reading the content of read only register, chip_id in reg 00h . it is not possible to read the vco subsystem version. 1.10 serial port the spi protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. wide compatibility with multiple protocols from multiple vendors c. simultaneous write/read during the spi cycle d. 5-bit address space e. 3 wire for write only capability, 4 wire for read/write capability typical serial port operation can be run with sclk at speeds up to 50 mhz. 1.10.1 serial port initialization at power-up at power-up, it is required that both sen and sck lines are initially held low, and that the frst rising edge occurs on the sck line before any rising edges occur on the sen line. if the frst rising edge occurs on the sen line before it does on the sck line the HMC832LP6GE spi interface will not function. in that case it is necessary to cycle the power to the off and on and repeat the recommended sequence above (hold both signals low at power-up and ensure that the frst rising edge occurs on the sck line). 1.10.2 serial port write operation avdd = dvdd = 3v, agnd = dgnd = 0v table 5. spi write timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk 32 rising edge to sen rising edge 10 ns t 6 recovery time 20 ns max serial port clock speed 50 mhz a typical write cycle is shown in figure 48 . a. the master (host) places 24-bit data, d23:d0, msb frst, on sdi on the frst 24 falling edges of sclk. b. the slave (HMC832LP6GE) shifts in data on sdi on the frst 24 rising edges of sclk www.datasheet.net/ datasheet pdf - http://www..co.kr/
40 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com c. master places 5-bit register address to be written to, r4:r0, msb frst, on the next 5 falling edges of sclk (25-29) d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master places 3-bit chip address, a2:a0, msb frst, on the next 3 falling edges of sclk (30-32). hittite reserves chip address a2:a0 = 000 for all rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32). g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. figure 48. serial port timing diagram - write 1.10.3 serial port read operation a typical read cycle is shown in figure 49 . in general, the ld_sdo line is always active during the write cycle. during any spi cycle ld_sdo will contain the data from the current address written in reg0h[7:3]. if reg0h[7:3] is not changed then the same data will always be present on ld_sdo when an open mode cycle is in progress. if it is desired to read from a specifc address, it is necessary in the frst spi cycle to write the desired address to reg0h[7:3], then in the next spi cycle the desired data will be available on ld_sdo. an example of the two cycle procedure to read from any random address is as follows: a. the master (host), on the frst 24 falling edges of sclk places 24-bit data, d23:d0, msb frst, on sdi as shown in figure 49 . d23:d5 should be set to zero. d4:d0 = address of the register to be read on the next cycle. b. the slave (HMC832LP6GE) shifts in data on sdi on the frst 24 rising edges of sck c. master places 5-bit register address , r4:r0, (the read address register), msb frst, on the next 5 falling edges of sck (25-29). r4:r0=00000. d. slave shifts the register bits on the next 5 rising edges of sck (25-29). e. master places 3-bit chip address, a2:a0, msb frst, on the next 3 falling edges of sck (30-32). chip address is always 000b. f. slave shifts the chip address bits on the next 3 rising edges of sck (30-32). g. master asserts sen after the 32nd rising edge of sck. h. slave registers the sdi data on the rising edge of sen. i. master clears sen to complete the the address transfer of the two part read cycle. j. if one does not wish to write data to the chip at the same time as we do the second cycle , then it is www.datasheet.net/ datasheet pdf - http://www..co.kr/
41 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz recommended to simply rewrite the same contents on sdi to register zero on the read back part of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling edges of sck. l. slave (HMC832LP6GE) shifts the sdi data on the next 32 rising edges of sck. m. slave places the desired read data (ie. data from the address specifed in reg 00h [7:3] of the frst cycle) on ld_sdo which automatically switches to sdo mode from ld mode, disabling the ld output. m. master asserts sen after the 32nd rising edge of sck to complete the cycle and revert back to lock detect on ld_sdo. table 6. spi read timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sck rising edge 3 ns t 2 sck rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sck rising edge to sdo time 8.2ns+0.2ns/pf ns t 6 recovery time 10 ns t 7 sck 32 rising edge to sen rising edge 10 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/
42 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com figure 49. serial port timing diagram - read for more information on using the gpo pin while in spi open mode please see section 1.10. www.datasheet.net/ datasheet pdf - http://www..co.kr/
43 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 2.0 pll register map 2.1 reg 00h id register (read only) bit type name width default description [23:0] ro chip_id 24 a7975 HMC832LP6GE chip id 2.2 reg 00h open mode read address/rst strobe register (write only) bit type name width default description [4:0] wo read address 5 - (write only) read address for next cycle - open mode only [5] wo soft reset 1 - soft reset - both spi modes reset (set to 0 for proper operation) [23:6] wo not defned 18 - not defned (set to 0 for proper operation) 2.3 reg 01h rst register (default 000002h) bit type name width default description [9:0] r/w rst_chipen_pin_select 1 0 1 = take pll enable via cen pin, see power down mode description 0 = take pll enable via spi (rst_chipen_from_spi) reg01[1] [1] r/w rst_chipen_from_spi 1 1 spis pll enable bit [9:2] r/w reserved 8 0 reserved 2.4 reg 02h refdiv register (default 000001h) bit type name width default description [13:0] r/w rdiv 14 1 reference divider r value (eq 12)) divider use also requires refbufen reg08[3]=1and divider min 1d max 16383d 2.5 reg 03h frequency register - integer part (default 000019h) bit type name width default description [18:0] r/w integer divider register 19 25d vco divider integer part, used in all modes, see (eq 12) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d integer mode min 16d max 2 19 -1 = 7ffffh = 524,287d www.datasheet.net/ datasheet pdf - http://www..co.kr/
44 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 2.6 reg 04h frequency register - fractional part (default 000000h) bit type name width default description [23:0] r/w frac 24 0 vco divider fractional part (24-bit unsigned) see fractional frequency tuning used in fractional mode only (n frac = reg 04h /2 24 min 0d max 2 24 -1 2.7 reg 05h vco spi register (default 000000h) bit type name width default description [2:0] r/w vco subsystem_id, 3 0 internal vco subsystem id [6:3] r/w vco subsystem register address 4 0 for interfacing with the vco please see section 1.3.1 . [15:7] r/w vco subsystem data 9 0 data to be written to the vco subsystem. note: reg05h is a special register used for indirect addressing of the vco subsystem. writes to reg 05h are automatically forwarded to the vco subsystem by the vco spi state machine controller. reg05h is a read-write register. however, reg05h only holds the contents of the last transfer to the vco subsystem. hence it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. please take note special considerations for autocal related to reg 05h 2.8 reg 06h delta sigma confguration register (default 200b4ah) bit type name width default description [1:0] r/w seed 2 2 selects the seed in fractional mode 00: 0 seed 01: lsb seed 02: b29d08h seed 03: 50f1cdh seed note; writes to this register are stored in the HMC832LP6GE and are only loaded into the modulator when a frequency change is executed and if autoseed reg06h[8] =1 [6:2] r/w reserved 5 18d reserved [7] r/w frac_bypass 1 0 0: use modulator, required for fractional mode, 1: bypass modulator, required for integer mode note: in bypass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [10:8] r/w initialization 3 3d program to 7d [11] r/w sd enable 1 1 0: disable frac core, use for integer mode or integer mode with csp 1: enable frac core, required for fractional mode, or integer isolation testing this register controls whether autocal starts on an integer or a fractional write [20:12] r/w reserved 9 0 reserved [21] r/w auto clock confguration 1 1 program to 0 [22] r/w reserved 1 0 reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
45 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 2.9 reg 07h lock detect register (default 00014dh) bit type name width default description [2:0] r/w lkd_wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/w enable internal lock detect 1 1 see section 1.10 serial port [5:4] r/w reserved 2 0 reserved [6] r/w lock detect window type 1 1 lock detection window timer selection 1: digital programmable timer 0: analog one shot, nominal 10 ns window [9:7] r/w ld digital window duration 3 2 0 lock detection - digital window duration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/w ld digital timer frequency control 2 0 lock detect digital timer frequency control 00 fastest, 11 slowest. see section 1.5.5 lock detect for more information. [12] r/w reserved 31 0 reserved [13] r/w auto relock - one try 1 0 1: attempts to relock if lock detect fails for any reason only tries once. 2.10 reg 08h analog en register (default c1beffh) bit type name width default description [4:0] r/w reserved 5 31d reserved [5] r/w gpo_pad_en 1 1 0 - pin ld_sdo disabled 1 - and regfh[7]=1 , pin ld_sdo is always driven, this is required for use of gpo port 1 - and regfh[7]=0 spi ldo_spi is off if unmatched chip address is seen on the spi, allowing a shared spi with other compatible parts [9:6] r/w reserved 4 11d reserved [10] r/w vco buffer and prescaler bias enable 1 1 vco buffer and prescaler bias enable [20:11] r/w reserved 1 55d reserved [21] r/w high frequency reference 1 0 program to 1 for xtal > 200 mhz [23:22] r/w reserved 2 3d reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
46 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 2 .11 reg 09h charge pump register (default 403264h) bit type name width default description [6:0] r/w cp dn gain 7 100d 64h charge pump dn gain control 20 astep affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [13:7] r/w cp up gain 7 100d 64h charge pump up gain control 20 a per step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [20:14] r/w offset magnitude 7 0 charge pump offset control 5 a/step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 10 a ... 127d = 635 a [21] r/w offset up enable 1 0 recommended setting = 1 in fractional mode, 0 otherwise [22] r/w offset dn enable 1 1 recommended setting = 0 [23] r/w reserved 1 0 reserved 2.12 reg 0ah vco autocal confguration register (default 002205h) bit type name width default description [2:0] r/w vtune resolution 3 5 r divider cycles 0 - 1 1 - 2 2 - 4 ... 7 - 256 [9:3] r/w reserved 7 72d reserved [10] r/w force curve 1 0 force curve sent during tuning tune from reg5 [11] r/w autocal disable 1 0 1 = autocal disabled [12] r/w no vspi trigger 1 0 dont trigger a transfer on writes to reg 05h [14:13] r/w fsm/vspi clock select 2 1 set the autocal fsm and vspi clock (50 mhz maximum) 0: input crystal reference 1: input crystal reference/4 2: input crystal reference/16 3: input crystal reference/32 [16:15] r/w reserved 2 0 reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
47 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 2.13 reg 0bh pd register (default 0f8061h) bit type name width default description [2:0] r/w pd_del_sel 3 1 sets pd reset path delay (recommended setting 001) [4:3] r/w reserved 2 0 reserved [5] r/w pd_up_en 1 1 enables the pd up output [6] r/w pd_dn_en 1 1 enables the pd dn output [8:7] r/w csp mode 2 0 cycle slip prevention mode extra current is driven into the loop flter when the phase error is larger than: 0: disabled 1: 5.4ns 2: 14.4ns 3: 24.1ns this delay varies by +- 10% with temperature, and +- 12% with process. [9] r/w force cp up 1 0 forces cp up output on - use for test only [10] r/w force cp dn 1 0 forces cp dn output on - use for test only [23:11] r/w reserved 13 496d 1f6h reserved 2.14 reg 0ch exact frequency mode register (default 000000h) bit type name width default description [13:0] r/w number of channels per fpd 14 0 comparison frequency divided by the correction rate, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: disabled 1: disabled 2:16383d (3fffh) www.datasheet.net/ datasheet pdf - http://www..co.kr/
48 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com 2.15 reg 0fh gpo_spi_rdiv register (default 000001h) bit type name width default description [4:0] r/w gpo_select 5 1d signal selected here is output to sdo pin when enabled 0: data from reg0f[5] 1: lock detect output 2. lock detect trigger 3: lock detect window output 4: ring osc test 5. pullup hard from csp 6. pulldn hard from csp 7. reserved 8: reference buffer output 9: ref divider output 10: vco divider output 11. modulator clock from vco divider 12. auxiliary clock 13. aux spi clock 14. aux spi enable 15. aux spi data out 16. pd dn 17. pd up 18. sd3 clock delay 19. sd3 core clock 20. autostrobe integer write 21. autostrobe frac write 22. autostrobe aux spi 23. spi latch enable 24. vco divider sync reset 25. seed load strobe 26.-29 not used 30. spi output buffer en 31. soft rstb [5] r/w gpo test data 1 0 1 - gpo test data [6] r/w prevent automux sdo 1 0 1- outputs gpo data only 0 - automuxes between sdo and gpo data [7] r/w ldo driver always on 1 0 1- ld_sdo pin driver always on 0 - ld_sdo pin driver only on during spi read cycle [8] r/w disable pfet 1 0 [9] r/w disable nfet 1 0 2.16 reg 10h vco tune register (default 000020h) bit type name width default description [7:0] ro vco switch setting 8 32 read only register. indicates the vco switch setting selected by the autocal state machine to yield the nearest free running vco frequency to the desired operating frequency. not valid when reg10h[8] = 1, autocal busy. note if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 256 = lowest frequency note: vco subsystems may not use all the msbs, in which case the unused bits are dont care [8] ro autocal busy 1 0 busy when autocal state machine is searching for the nearest switch setting to the requested frequency. www.datasheet.net/ datasheet pdf - http://www..co.kr/
49 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 2.17 reg 11h sar register (default 007fffh) bit type name width default description [18:0] ro sar error mag counts 19 2 19 -1 sar error magnitude counts [19] ro sar error sign 1 0 sar error sign 0=+ve 1=-ve 2.18 reg 12h gpo2 register (default 000000h) bit type name width default description [0] ro gpo 1 0 gpo state [1] ro lock detect 1 0 lock detect status 1 = locked 0 = unlocked 2.19 reg 13h bist register (default 000000h) bit type name width default description [16:0] ro reserved 17 4697d reserved 3.0 vco subsystem register map please note that the vco subsystem uses indirect addressing via reg 05h . for more detailed information on how to write to the vco subsystem please see section 1.3.1 vco serial port interface (vspi) . 3.1 vco_reg 00h tuning bit type name width default description [0] wo cal 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage [8:1] wo caps 8 16 vco sub-band selection. 0 - max frequency 1111 1111 - min fre quen cy. 3.2 vco_reg 01h enables bit type name width default description [0] wo master enable vco subsystem 1 1 0 - all vco subsystem blocks off [1] wo vco enable 1 1 enables vcos [2] wo pll buffer enable 1 1 enables pll buffer to n divider [3] wo io master enable 1 1 enables output stage and the output divider. it does not enable/disable the vco. [4] wo reserved 1 1 reserved [5] wo output stage enable 1 1 output stage enable [7:6] wo reserved 2 2 reserved [8] wo reserved 1 1 reserved for example, to disable the output stage of the vco subsystem of the HMC832LP6GE, bit 5 in vco_reg 01h needs to be cleared. if the other bits are left unchanged, then 1 1101 1111 needs to be written into vco_reg 01h . the vco subsystem register is accessed via a write to pll subsystem reg 05h = 1 1101 1111 0001 000 = ef88h reg 05h [2:0] = 000; vco subsystem id 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
50 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com reg 05h [6:3] = 0001; vco subsystem register address reg 05h [7] = 1; master enable reg 05h [8] = 1; vco enable reg 05h [9] = 1; pll buffer enable reg 05h [10] = 1; io master enable reg 05h [11] = 1; reserved reg 05h [12] = 0; disable the output stage reg 05h [14:13] = 01b reg 05h [15] = 1; dont care 3.3 vco_reg 02h vco output divider bit type name width default description [5:0] wo rf divide ratio 6 1 0 - mute the output when vco_reg 03h [8:7] = 0d 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 [8:6] wo reserved 3 0 reserved for example, to write 0_1111_1110 into vco_reg 02h vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to reg 05h =0 _1111_1110, 0 010, 0 0 0 b. reg 05h [2:0] = 000; subsystem id 0 reg 05h [6:3] = 0010; vco register address 2d reg 05h [16:7] = 0 _1111_1110 ; divide by 62, max output rf gain www.datasheet.net/ datasheet pdf - http://www..co.kr/
51 plls with integrated vco - smt for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz 3.4 vco_reg 03h confg bit type name width default description [1:0] wo programmable performance mode 2 2 selects output noise foor performance level at a cost of increased current consumption 01: low current consumption mode 11: high performance mode other states (00 and 10) not supported. [2] wo rf_p output enable 1 0 enables the output on rf_p pin. required for differential operation, or single-ended output on rf_p pin. [3] wo rf_n output enable 1 0 enables the output on rf_n pin. required for differential operation, or single-ended output on rf_n pin. [4] wo reserved 1 1 reserved [5] wo return loss 1 0 0: return loss = -5 db typical. (highest output power) 1: return loss = -10 db typical [6] wo reserved 1 0 reserved [8:7] wo mute mode 2 1 defnes when the mute function is enabled (the output is muted), see section 1.4.4 , and figure 35 for more information: ? 00: mute enabled when divide ratio ( vco_reg 02h [5:0] = 0. this enables the HMC832LP6GE to be backwards compatible to hmc830lp6ge mute function. ? 01: during vco calibration (see 1.4.1 vco calibration section for more details) ? 10: not supported ? 11: mute all rf outputs (unconditional) 3.5 vco_reg 04h cal/bias specifed performance is only guaranteed with the required settings in this table. other settings are not supported. bit type name width default description [0] wo initialization 9 201d program to 193d 3.6 vco_reg05h cf_cal bit type name width default description [8:0] wo reserved 9 170d reserved 3.7 vco_reg06h msb cal bit type name width default description [8:0] wo reserved 9 255d reserved 3.8 vco_reg 07h output power control bit type name width default description [3:0] wo output stage gain control 4 1 output stage gain control in 1 db steps. 0d: 0 db gain 1d: 1 db gain 2d: 2 db gain ... 10d: 10 db gain 11d: 11 db gain [4] wo initialization 1 0 program to 1 [8:5] wo reserved 4 7d reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
52 plls with integrated vco - smt HMC832LP6GE v01.0812 fractional-n pll with integrated vco 25 - 3000 mhz for price, delivery, and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/

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